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[answered] Memory Access Impact on Performance: Assume that main memor


Can you solve this assignment based on cache hits and misses?


Memory Access Impact on Performance:

 

Assume that main memory accesses take 80 ns and that memory accesses are 42% of all

 

instructions. The L1 cache has a miss rate of 9% and a hit time of 0.58 ns.

 

1.Assume that the L1 hit time determines the cycle time for the processor.

 

What is the clock rate?

 

1._______

 

2.What is the Average Memory Access Time for the processor?

 

2.________

 

3.Assuming a base CPI of 1.0 without any memory stalls (once the pipeline is

 

loaded), what is the total average CPI for the processor?

 

3. _______

 

We will consider the addition of an L2 cache to try to reduce the average CPI; on a miss, P1 will

 

now first check L2 cache, and only if that is a miss, will then need a main memory access.

 

The L2 miss rate is 85%, and L2 hit time is 4.88ns

 

4.What is the AMAT for the processor, with the inclusion of the L2 cache?

 

4._________

 

5. Assuming a base CPI of 1.0 without any memory stalls, and using the

 

same instruction miss as part 1 of this question, what is the total CPI (for

 

all instruction types) for P1 with the addition of an L2 cache? 5._________ Question #1: The cache for this problem has 16 words. You are going to evaluate the cache

 

performance based on different mapping schemes, and different size blocks, to try to come up

 

with the best mapping and block arrangement for this series of memory access calls.

 

Your mappings will be:

 

16 one-word blocks, Direct Mapping

 

16 one-word blocks, Fully Associative Mapping

 

4 4-word blocks, Direct Mapping

 

4 4-word blocks, Fully Associative Mapping

 

4-way Set-Associative, 16 one-word blocks

 

For each of the schemes,

 

1. Fill out the ?top? table of ?tags?

 

2. Show the placement of the block in the ?bottom? table

 

3. Count the ?hits? and ?misses?

 

4. Compare the hit/miss ratios for the different mappings and block arrangements

 

If you were designing the cache, what do you think would have to most impact on the

 

performance: larger block sizes, or different mapping schemes? Explain your reasoning. Word

 

Address

 

2

 

3

 

11

 

16

 

21

 

13

 

64

 

48

 

19

 

11

 

3

 

22

 

4

 

27

 

6

 

11 Word

 

Bit Address

 

00000010

 

00000011

 

00001011

 

00010000

 

00010101

 

00001101

 

01000000

 

00110000

 

00010011

 

00001011

 

00000011

 

00010110

 

00000100

 

00011011

 

00000110

 

00001011 # hits : # misses Direct 16

 

Tag Direct 4

 

Tag Fully Assoc.

 

16 Tag Fully Assoc.

 

4 _________ ________ _________ _________ CAT size in bits:

 

16 Blocks

 

0 (0000)

 

1 (0001)

 

2 (0010)

 

3 (0011)

 

4 (0100)

 

5 (0101)

 

6 (0110)

 

7 (0111)

 

8 (1000)

 

9 (1001)

 

10 (1010)

 

11 (1011)

 

12 (1100)

 

13 (1101)

 

14 (1110)

 

15 (1111) Direct Map

 

Associative

 

1word blocks 1word blocks 4 Blocks 0 (00) 1 (01) 2 (10) 3 (11) Direct Map

 

Associative

 

4-word block 4-word block 4-way Set Associative with 1-word blocks

 

Word

 

Address

 

2

 

3

 

11

 

16

 

21

 

13

 

64

 

48

 

19

 

11

 

3

 

22

 

4

 

27

 

6

 

11 Word

 

Bit Address

 

00000010

 

00000011

 

00001011

 

00010000

 

00010101

 

00001101

 

01000000

 

00110000

 

00010011

 

00001011

 

00000011

 

00010110

 

00000100

 

00011011

 

00000110

 

00001011 4 way set

 

Tag # hits : # misses ____________ CAT size in bits: ____________ 4 way sets Slot 2 0 (00) 1 (01) 2 (10) 3 (11) Slot 1 Slot 3 Slot 4

 


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