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Answered: - CS 2011 April 5th, 2016 CS 2011: Midterm II Spring


Dear Course Tutors

So I have this take home assignment due next week, I already completed Q1 so I just need Q2 and Q3 Asap. Thanks


CS 2011

 


 

April 5th, 2016

 


 

CS 2011: Midterm II

 


 

Spring 2014

 

Instructor: Professor Eric Rozier

 


 

Question:

 


 

1

 


 

2

 


 

3

 


 

Total

 


 

Points:

 


 

20

 


 

35

 


 

45

 


 

100

 


 

Score:

 


 

Answer the questions in the spaces provided. If you run out of room for an answer,

 

continue on the back of the page.

 


 

UNIVERSITY OF CINCINNATI HONOR PLEDGE

 

I have neither given nor received unauthorized aid on this piece of work, and I understand and will uphold

 

the ideals of academic honesty as stated in the Honor Code.

 


 

Printed name:

 

Signature:

 


 

CS 2011

 


 

Name:

 


 

1. PYTHIAS Inc, a company which builds branch prediction units has consulted you about a new processor

 

they are designing.

 

[10]

 


 

(a) The processor has allocated a single bit for a special type of ?smart branch? instruction which the

 

compiler will set to indicate, for branches, if the branch is associated with a loop or with an if

 

statement. What is a good default prediction for loops? What is a good default prediction for ifs?

 

Why?

 


 

[5]

 


 

(b) Describe a way that dynamic branch prediction might help PYTHIAS better predict the result an

 

if statement that is normally true.

 


 

[5]

 


 

(c) Branch prediction improves pipelining stalls due to what type of hazard?

 


 

Midterm II

 


 

April 5th, 2016

 


 

CS 2011

 


 

Name:

 


 

2. Assume a processor with a ?ve stage pipeline which has the following phases: Fetch, Decode, Execute,

 

Memory, Writeback.

 

[10]

 


 

(a) Given the instruction add r1, r1, r2 what happens during each stage?

 


 

[10]

 


 

(b) Given the instruction str r2, [r1, #0] what happens during each stage?

 


 

[15]

 


 

(c) For the following sequence of instructions, draw the reservation table for the pipeline, and identify

 

all hazards. Assume separate program and data memories (meaning that instruction fetches do

 

not stall when loading data from memory). Assume all stages of the pipeline take a single cycle to

 

complete.

 

ldr r1, [r1, #0]

 

add r1, r1, r2

 

ldr r2, [r1, #0]

 

or r3, r1, r2

 


 

Midterm II

 


 

April 5th, 2016

 


 

CS 2011

 


 

Name:

 


 

3. Consider the following C code, and assembly code for an interesting function.

 

int rofl(int a, int b, int size, int *c) {

 

if ((____) __ (____)) {

 

int tmpA = ____;

 

int tmpB = ____;

 

____ = tmpB;

 

____ = tmpA;

 

} else {

 

_________;

 

}

 

________;

 

}

 


 

0x0c04

 

0x0c04

 

0x0c08

 

0x0c0c

 

0x0c10

 

0x0c14

 

0x0c18

 

0x0c1c

 

0x0c20

 

0x0c24

 

0x0c28

 

0x0c2c

 

0x0c30

 

0x0c34

 

0x0c38

 

0x0c3c

 

0x0c40

 

0x0c44

 

0x0c48

 

0x0c4c

 


 

<rofl>:

 

push {r4-r9, lr}

 

mov r4, r0

 

mov r5, r1

 

mov r6, r2

 

mov r7, r3

 

cmp r4, r6

 

bhs 0x0c44

 

cmp r5, r6

 

bhs 0x0c44

 

ldr r8, [r7, r4]

 

ldr r9, [r7, r5]

 

str r8, [r7, r5]

 

str r9, [r7, r4]

 

mov r0, #1

 

pop {r4-r9, lr}

 

mov pc, lr

 

mvn r0, #1

 

pop {r4-r9, lr}

 

mov pc, lr

 


 

[30]

 


 

(a) Using your knowledge of C and assembly, ?ll in the blanks above with the appropriate expressions.

 


 

[8]

 


 

(b) Explain what the assembly code on lines 0x0c04, 0x0c3c, and 0x0c48 are doing, and why they are

 

necessary.

 


 

[7]

 


 

(c) Why does the code on line 0x0c38 and 0x0c44 assign a value to r0 if the function never uses it?

 


 

Midterm II

 


 

April 5th, 2016

 


 

 


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